Hybrid bonding is the part of last weekend’s chip news that most headlines skipped. This one takes a little more explaining than usual, so stay with me. On October 10, CXMT, China’s largest maker of DRAM memory chips, said it will launch server memory built on a new “4F²” cell design before the end of 2026, Seoul Economic Daily reported. Samsung has already shown a similar chip, and it is aiming for 2028. The gap between those two dates mostly comes down to one manufacturing step.
First, what 4F² means. DRAM stores each bit of data in a tiny cell: a capacitor that holds an electric charge, plus a transistor that works as an on-off switch. “F” is the thinnest line a factory can draw on a chip. Today’s standard cell covers an area of 6F², or six of those squares. A 4F² cell covers four. Same line width, a third less area per cell, and roughly 50% more cells in the same space.
To get there, the switch has to change shape. Instead of lying flat beside the capacitor, the transistor stands up as a small vertical pillar, with the gate (the part that turns it on and off) wrapped all the way around it. CXMT calls its version a Vertical Surrounded Gate transistor.
This matters a lot for China. The usual way to pack in more cells is to draw thinner lines, and the best tools for that are ASML’s EUV lithography machines, which Chinese companies cannot buy because of export controls. I wrote about how hard it is to rebuild that kind of equipment from parts in the tacit knowledge piece. Changing the shape of the cell is a way to gain density without winning the thin-line race.
Now the step that decides the timeline. A memory chip has two areas. One is the cell array, where the data lives. The other is the peripheral circuitry, the logic that reads, writes and routes the data. For decades both were built on the same wafer, with the same process. That was always a compromise, because the cell array and the logic want different things. With vertical cells packed this tightly, the logic also runs out of room beside the array. The cleaner answer is to put it underneath.
That is what the bonding step does. The cell array is made on one wafer and the logic on another. Then one wafer is flipped face-down onto the other, and millions of tiny copper pads are fused directly to each other, with no solder bumps in between. Think of printing the front and back of a page on two separate sheets, then laminating them so that every letter lines up exactly, at a scale far thinner than a human hair. Each side can be made with the process that suits it. But the alignment and the bond have to be close to perfect across the whole wafer.
Samsung showed a 16Gb prototype earlier this year that combined 4F² cells with this wafer-to-wafer approach. Its public target for mass production is 2028.
What CXMT said, and what it didn’t. According to Yicai, the approaches at the heart of the design CXMT President Cao Kanyu presented are building the cell array apart from the logic, and joining the two with wafer-level hybrid bonding. Cao also said CXMT holds more than 300 published patent families on 4F² designs. So this is not a sudden claim. The company has been publishing 4F² research for years.
What CXMT did not share are the numbers that matter for servers. There is no yield figure (how many good chips come off each wafer). There is no retention figure either. Retention is how long a cell keeps its charge before it has to be refreshed. Vertical transistors have a known weak spot here: unwanted charge can build up inside the pillar and make cells leak faster. A server runs 24 hours a day, so leaky cells mean more refreshing, more power and slower memory. On top of that, Money Today reported that the first products may use 4F² only in part. And “launching” a product is not the same as making it in high volume.
Why Korea is watching. CXMT is already the fourth-largest DRAM maker, with a 9.5% revenue share in the second quarter, behind Samsung (39.4%), SK hynix (24.9%) and Micron (23.3%), according to TrendForce. Until now, most of its chips went into phones and PCs. Server memory is where Samsung and SK hynix earn much of their profit, and where the rivalry is already tight, as I covered in the HBM standards war post. Even a partial 4F² server module changes the story investors tell about who is catching up with whom. A story can move stock prices long before a product moves market share.
So the question is not whether CXMT can draw a 4F² cell. It clearly can. The question is whether it can bond the two halves of the chip at a good yield, and keep the cells from leaking, by December.
My take: The date has been announced. The glue hasn’t been shown.
Not advice. Just how I see it.